In a memory test system for testing semiconductor memory devices, a test data pattern is provided to a memory device under test and a resultant output from the memory device is compared with an expected value pattern established in advance to determined whether the memory device under test works correctly or not. The results of the test are stored in a fail memory with respect to each address of the memory device under test types of fail and other information regarding the memory device under test.
In a high speed memory test system, time divisional technique (data multiplex mode) is utilized to increase the test speed wherein a plurality of test data patterns are applied to the memory device under test within each test cycle. The test cycle is a basic rate of the memory test system for which a normal test operation is performed. In the data multiplex mode, two or more test patterns in parallel are multiplexed in a time sequential manner to produce a series test pattern whose data rate is two or more times higher than the test cycle.
An example of such a memory test system in the conventional technology is shown in FIGS. 3 and 4. FIG. 3 is a block diagram showing a basic structure of such a conventional memory test system. FIG. 4 is a timing chart showing the operation of the memory test system of FIG. 3. In the timing chart of FIG. 4, the data multiplex mode (first and second test cycles) and the normal test mode (third and fourth test cycles) are shown to illustrate the operational differences between the two modes. Further, the timing chart of FIG. 4 is a simplified illustration of the test data and expected value data with respect to the test cycles and thus the detailed timings or phase delays are not accurately described.
As shown in FIG. 3, the conventional memory test system includes an algorithmic pattern generator (ALPG) 10, a programmable data selector (PDS) 20, a wave formatter circuit 30, an expected value select circuit 40, a logic comparator 50, a driver 61 and an analog comparator 62. Typical semiconductor memories to be tested (MUT) by the memory test system include dynamic random access memories (DRAM) and static random access memories (SRAM).
The ALPG 10 is a pattern generator which is capable of generating a test pattern of mathematical sequence to test a memory device 70. The test pattern includes a data pattern for testing the memory device 70 under test and a pattern select signal PATSEL for selecting the data pattern to be applied to the memory device 70.
The PDS 20 selectively assigns the data pattern from the ALPG 10 to a plurality of ports, in this example, a port A and a port B for each test cycle. As shown in FIGS. 4A and 4B, in the normal mode (third and fourth cycles), an identical data pattern is produced at the ports A and B. In the data multiplex mode (first and second cycles), different data patterns PATA and PATB are respectively produced at the ports A and B in a parallel fashion.
The wave formatter circuit 30 is to format the waveform of the data pattern to be supplied to the memory device 70 under test. For example, as is known in the art, the wave formatter produces either a return to zero (RZ) waveform, a non-return to zero (NRZ) waveform or an exclusive OR (EOR) waveform. As shown in FIG. 3, the wave formatter circuit 30 includes a multiplexer 31 and a formatter 32. The multiplexer 31 selects one of the data patterns from the ports A and B based on the pattern select signal PATSEL. The formatter 32 produces the above noted waveforms.
In the data multiplex mode, the pattern select signal PATSEL of FIG. 4C changes the state within the test cycle so that the data patterns PATA and PATB are alternately selected within the test cycle as shown in FIG. 4D. As a consequence of this time divisional operation, a test signal pattern having two data patterns in one test cycle as shown in FIG. 4D can be generated by the wave formatter 30.
In FIG. 3, the test data pattern from the wave formatter 30 is provided to the driver 61 wherein the amplitude is regulated for the test purpose and is applied to the memory device 70. An output voltage level of the memory device 70 is compared with reference voltages (not shown) by the analog comparator 62 to determine whether the output signal of the memory 70 in response to the test data is logic "1" or logic "0". Thus, the output of the analog comparator 62 as shown in FIG. 4E is provided to the logic comparator 50 wherein it is compared with the expected value data as described in more detail below.
The expected value select circuit 40 includes a multiplexer 41 and a register 43. Generally, in testing memory devices, expected value data is the same as the data pattern that is written in the memory device under test because the resultant data from the memory device should be the test data read out from the memory device. Thus, the multiplexer 41 selects one of the test data patterns from the port A or B based on the data from the register 43. In the conventional memory test system of FIG. 3, in either the multiplex mode or the normal mode, only one of the data patterns is used as expected value data.
The logic comparator 50 receives the output of the memory device 70 under test through the analog comparator 62 and compares the logic state of the output of the memory device 70 with the expected value data. In this example, the logic comparator 50 includes latches 51 and 52 and exclusive OR gates 53 and 54. As is well known in the art, the exclusive OR gate detects whether the two incoming signals coincide with each other.
The latches 51 and 52 receive the device logic output from the analog comparator 62 and latch the device logic output signal at the timings of strobe signals. The output of the latch 51 is connected to an input of the exclusive OR gate 53 while the output of the latch 52 is connected to an input of the exclusive OR gate 54. The output of the expected value select circuit 40 is connected to the other inputs of the exclusive OR gates 53 and 54.
A strobe signal STRB.sub.1 is provided to the latch 51 to latch the device logic output at the timing of the strobe signal STRB.sub.1. The latched logic output shown in FIG. 4G from the latch 51 is compared with the expected value data by the exclusive OR gate 53. A strobe signal STRB.sub.2 is provided to the latch 52 to latch the device logic output at the timing of the strobe signal STRB.sub.2. The latched logic output shown in FIG. 4H from the latch 52 is compared with the expected value data by the exclusive OR gate 54. The timings of the strobe signals are so regulated as shown in FIG. 4F that the strobe signal STRB.sub.1 can latch the first half of the output signal of the memory device and the strobe signal STRB.sub.2 can latch the last half of the output signal of the memory device within one test cycle.
However, in the data multiplex mode shown in the first two test cycles of FIG. 4, the conventional memory test system cannot perform two comparison operations within one test cycle in the data multiplex mode. This is because the expected value data of FIG. 4I from the expected value select circuit 40 is not multiplexed in real time as noted above. Therefore, it is necessary to carry out two test procedures to complete the test.
Namely, in the first test procedure, the logic output (PATA) of FIG. 4G is compared with the expected value data (PATA) of FIG. 4I by the timing of the strove signal STRB.sub.1. After all the test is done for the logic output of FIG. 4G, in the second test procedure, the logic output (PATB) of FIG. 4H is compared with the expected value data (PATB) shown in the hatched portion of FIG. 4I by the timing of the strove signal STRB.sub.2.
As in the foregoing, in the conventional memory test system, two or more test patterns can be supplied to the memory device under test within one test cycle to test the high speed memory device. However, in comparing the output of the memory device under test, it is not possible to perform two operations within one test cycle, since two or more different expected value patterns cannot be obtained within the one test cycle. Therefore, to complete the memory device test, it is necessary to repeat two or more test procedures as noted above by changing the expected value data, which results in a long test time.